In large ASIC (Application Specific Integrated Circuit) and Gate Array designs, an ECO (Engineering Change Order) is often performed to make small modifications to an already completed (or almost completed) IC design. A net is a set of two or more pins which must be connected, thus connecting the logic circuits having the pins. Currently, there exists no method for detecting nets that have been physically changed or electrically affected by an ECO. However, such information may be important in reducing the runtime of CAD (Computer Aided Design) tools needed to re-analyze the post ECO design and in evaluating the efficacy of the method used to execute the ECO.
Thus, it would be desirable to provide a method and apparatus for determining the change (both physical and electrical) on the design wiring caused by an ECO.